Question

Six stage pipeline with clock rate 4.5 times faster than unpipelined clock, but 9% of the instructions need to stall for one cycle.

Answer 1

Answer:

Assume that the original machine is a 5-stage pipeline with a 1 ns clock cycle. The second machine is a 12-stage pipeline with a 0.6 ns clock cycle. The 5-stage pipeline experiences a stall due to a data hazard every 5 instructions, whereas the 12-stage pipeline experiences 3 stalls every 8 instructions.