Question

SOLVE THE TWO QUESTIONS BELOW IF YOU ARE BRAINLIEST. DONT SEND WRONG ANSWERS

1. For a supply voltage of 2.5 V, the normalized on-channel resistances of NMOS and
PMOS transistors equal 13 k Ω and 31 kΩ, respectively. From the layout, we determine
the (W/L) ratios of the transistors to be 1.5 for the NMOS, and 4.5 for the PMOS. Cint
= 3.0 fF, Cext = 3.15 fF. What scaling factor allows us to get within 10% of the optimal
performance (intrinsic performance).



2. In order to drive a large capacitance (CL = 100 pF) from a minimum size gate (with
input capacitance Ci = 25fF), (a) you decide to introduce a four-staged buffer. Assume
that the propagation delay of a minimum size inverter is 50 ps. Also assume that the
input capacitance of a gate is proportional to its size. Determine the sizing of the four
additional buffer stages that will minimize the propagation delay. (b) If you could add
any number of stages to achieve the minimum delay, how many stages would you
insert? What is the propagation delay in this case? (c) Describe the advantages and
disadvantages of the methods shown in (a) and (b).

Answer 1

Answer:

Please go through the attachment..

Explanation:

Hope it works. please mark me as brainliest. Thank you