Question

Suppose that in 1000 memory references there are 40 misses in the first-level cache and
20 misses in the second-level cache. What are the various miss rates? Assume the miss
penalty from L2 cache to Memory is 200 clock cycles, the hit time of L2 cache is 10 clock
cycles, the Hit time of L1 is 1 clqck cycle, and there are 1.5 memory references per
instruction. What is average memory access time and average stall cycles per instruction?
Ignore the impact of writes.
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Answer 1

Answer:

the difference 20.

Explanation:

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