Question

The block diagram of a frequency synthesizer

consisting of Phase Locked Loop (PLL) and a divideby-N counter (comprising ÷2, ÷4, ÷8, ÷16 outputs) is

sketched below. The synthesizer is excited with a 5 kHz

signal (Input 1). The free-running frequency of the PLL is

set to 20 kHz. Assume that the commutator switch makes

contacts repeatedly in the order 1-2-3-4.​

Answer 1

Explanation:

The block diagram of a frequency synthesizer

consisting of Phase Locked Loop (PLL) and a divideby-N counter (comprising ÷2, ÷4, ÷8, ÷16 outputs) is

sketched below. The synthesizer is excited with a 5 kHz

signal (Input 1). The free-running frequency of the PLL is

set to 20 kHz. Assume that the commutator switch makes

contacts repeatedly in the order 1-2-3-4.

Answer 2

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