Question

the following transfer statements specify a memory. explain the memory operation in each case.
a. R2<-M[AR]
b. M[AR]<-R3
c. R5<-M[R5]
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Answer 1

Answer:

b is the answer

Explanation:thank you you fool

Answer 2

Answer:

T0: R5 <--- R0

T1: R5 <--- R1

T2: R5 <--- R2

 T3: R5 <--- R3

    The timing variable are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal 0. Draw a block diagram showing the hardware implementation of the register transfers. Include the connection necessary from the four timing variables to the selection input of multiplexers and to the load input of register R5.

       Here we have used 4*1 MUX in this circuit R0, R1, R2, R3 are inputs and R5 is the outputs from each register 8 bit are passed two OR gate is connected to S0 to S

     

These are 4 timing variable T0, T1, T2, T3 which are mutually exclusion which means that only one variable is equal to 1 at any given time while the other there are equal to 0

Explanation:

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