The output from a NAND gate is divided into two in parallel
and fed to another NAND gate. The resulting gate is a
[NEET Kar. 2013]
(a) NOT gate (b) AND gate
(c) NOR gate (d) OR gate
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Explanation:
The output from a NAND gate is divided into two in parallel
and fed to another NAND gate. The resulting gate is a
[NEET Kar. 2013]
(a) NOT gate (b) AND gate
(c) NOR gate (d) OR gat
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