Question

The outputs of four registers, RO, Rl, R2. and R3, are c:xmne<.ted through

4-tc>-1-line multipleJ<erS to the inputs of a fifth register, RS. Each register is

eight bits long. The required transfers are dictated by four timing variables

To through T, as foUows:

To: RS+-RO

To: RS<-Rl

T,: R5<-R2

T,: RS+-R3

The timing variables are mutuaUy e>cclusive, which means that only one variable is equal to I at any given time, while the other tlwe are equal to

0. Draw a block diagram showing the hanfware Implementation of the

register transfers. Include the connections nettSSoll)' from the four timing

variables to the selection inputs of the multiplexers and to the load input of

register RS.​

Answer 1

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