The pointin cmos inverter where both transistos are in saturation
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We assume that the input to a CMOS gate is driven by another CMOS gate, and that the output of a CMOS gate is either at VDDVDD for a logic 1 or at ground for a logic 0. We also (usually) assume that the sources of all NMOS transistors are tied to ground and that the sources of all PMOS transistors are tied to VDDVDD.
Another simplifying assumption is that the inputs of the logic gate that you wish to analyze are stable and at either VDDVDD or ground. If the input is at VDDVDD then the PMOS transistors are cut off and we are only interested in what the NMOS transistors are doing. Since the NMOS source is at ground we use
VGSN=VG−VS=VDD−0=VDDVGSN=VG−VS=VDD−0=VDD
If you assume that the logic gate input is at ground then the NMOS is cut off and VGSP=−VDDVGSP=−VDD.
Of course, that's a lot of simplifying assumptions. The dynamic behaviour is much more complex, and the effective RDSRDS changes as the logic gate's output voltage (and hence the transistor's VDSVDS) changes. If you really want good answers, simulate in SPICE with accurate input rise/fall times and parasitic capacitances. For back-of-the envelope calculations you could approximate RDSRDS with something like twice the effective RDSRDS when VDS=VDDVDS=VDD but this would be really crude. The RMIDRMID in your first graph is another approximation using IDSIDS when VDS=VDD/2VDS=VDD/2.
The bottom graph that you provide illustrates dc behavior and isn't very relevant for transient switching behavior
Another simplifying assumption is that the inputs of the logic gate that you wish to analyze are stable and at either VDDVDD or ground. If the input is at VDDVDD then the PMOS transistors are cut off and we are only interested in what the NMOS transistors are doing. Since the NMOS source is at ground we use
VGSN=VG−VS=VDD−0=VDDVGSN=VG−VS=VDD−0=VDD
If you assume that the logic gate input is at ground then the NMOS is cut off and VGSP=−VDDVGSP=−VDD.
Of course, that's a lot of simplifying assumptions. The dynamic behaviour is much more complex, and the effective RDSRDS changes as the logic gate's output voltage (and hence the transistor's VDSVDS) changes. If you really want good answers, simulate in SPICE with accurate input rise/fall times and parasitic capacitances. For back-of-the envelope calculations you could approximate RDSRDS with something like twice the effective RDSRDS when VDS=VDDVDS=VDD but this would be really crude. The RMIDRMID in your first graph is another approximation using IDSIDS when VDS=VDD/2VDS=VDD/2.
The bottom graph that you provide illustrates dc behavior and isn't very relevant for transient switching behavior
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