Question

The register r5 has a 32-bit control information. bit[3] of this control information corresponds to enabling and disabling of caches. the register r5 has a value of 0xfecbca56. if bit[3] = 0, the caches are disabled and if bit[3] = 1, the caches are enabled. (note that bit[0] corresponds to lsb and bit[31] corresponds to msb of r5).

a. to enable the caches, read-modify-write sequence of r4 contents is required to make bit[3] = 1.

b. no operation required since bit[3] is already 1.

c. to enable the caches, only write sequence is sufficient to make bit[3] = 1.

d. to enable the caches, write-modify-read sequence of r4 contents is required to make bit[3] = 1.

Answer 1

The third field of the header consists of ------ bit Ethernet frame type