Tomasulo algorithm exercises with answer
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The out-of-order machine in this problem behaves as follows:
● The frontend of the machine has a one-cycle fetch stage and a one-cycle decode stage. The machine can fetch one instruction per cycle, and can decode one instruction per cycle.
● The machine dispatches one instruction per cycle into the reservation stations, in program order. Dispatch occurs during the decode stage.
● An instruction always allocates the first reservation station that is available (in top-to-bottom order) at the required functional unit.
● When a value is captured (at a reservation station) or written back (to a register) in this machine, the old tag that was previously at that location is not cleared; only the valid bit is set.
● When an instruction in a reservation station finishes executing, the reservation station is cleared.
● The frontend of the machine has a one-cycle fetch stage and a one-cycle decode stage. The machine can fetch one instruction per cycle, and can decode one instruction per cycle.
● The machine dispatches one instruction per cycle into the reservation stations, in program order. Dispatch occurs during the decode stage.
● An instruction always allocates the first reservation station that is available (in top-to-bottom order) at the required functional unit.
● When a value is captured (at a reservation station) or written back (to a register) in this machine, the old tag that was previously at that location is not cleared; only the valid bit is set.
● When an instruction in a reservation station finishes executing, the reservation station is cleared.
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