Question

#urgent_help
design asynchronous counter using jk flip for getting the following sequence 0-2-4-7-9-0​

Answer 1

Answer:

This is My answer

Explanation:

An “asynchronous” counter is one where the output of one flipflop is connected to the clock input of the next. The JK inputs are tied high.

You need to add decoding logic to the Q outputs to get the desired sequence. Since the sequence 0-2-4-7-9-0 has only 5 states, the counter must be reset as soon as it enters the 6th state (101) which is also decided by the decoding logic. That is what the clr input is for. It is an asynchronous reset.

Note that because there is a delay between excitation of a flip flop and its response, there will be glitches galore in this setup.