Question

We begin with a computer implemented in single-cycle implementation. When the stages are split by functionality,
the stages do not require exactly the same amount of time. The original machine had a clock cycle time of 7 ns. Afte
the stages were split, the measured times were JF (Intruction Fetch), 1 ns; ID (Instruction Decode), 1.5 ns; EX
(Execute), 1 ns; MEM, 2 ns; and WB (Write Back), 1.5 ns. The pipeline register delay is 0.1 ns. (a) What is the clock
cycle time of the 5-stage pipelined machine.
(b) If there is a stall every 4 instructions, what is the CPI of the new machine?
(c ) What is the speedup of the pipelined machine over the single-cycle machine?
(d) If the pipelined machine had an infinite number of stages, what would its speedup be over the single-cycle
machine?
[1 x 10= 1​

Answer 1

Explanation:

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