Question

what are called stals in computer architecture​

Answer 1

Explanation:

In the design of pipelined computer processors, a pipeline stall is a delay in execution of an instruction in order to resolve a hazard. ... It also stalls the instruction in the fetch stage, to prevent the instruction in that stage from being overwritten by the next instruction in the program

Answer 2

Answer:

In the design of pipelined computer processors, a pipeline stall is a delay in execution of an instruction in order to resolve a hazard. ... It also stalls the instruction in the fetch stage, to prevent the instruction in that stage from being overwritten by the next instruction in the program.