Question

What are the limitations of RS flip flop

Answer 1

Answer---

The one major disadvantage of the s-r flip flop is that in the condition when the clock is triggered the inputs become high which is an undesirable condition because it causes invalid input ,the condition in which you can't predict the output.

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Answer 2

Answer:

° The problem with simple SR flip-flop is that they are level sensitive to the control signal.

°Even though simple SR flip-flop and simple SR latches are same, both the terms are used in their respective contexts.

Explanation:

SR flip-flop can also be designed by cross-coupling of two  NOR gates. It is an active high input SR flip-flop.

→When both the SET and RESET inputs are low , then the output remains in previous states i.e., it holds the previous data.

→When SET input is low and RESET input is high, then the flip-flop will be RESET state. Because the input of NOR gate with R input drive the other NOR gate with O, as its output is O.

So both the inputs of the NOR gate with O input are S. This will cause the output of the flip-flop to settle in RESET state.

→When SET input is high and RESET input is low , the flip-flop will be in SET state. Because the low input of NOR gate with S input drive the other NOR gate with 1, as its output is 1. So both the inputs of the NOR gate with R input are 1. This will cause the output of the fliip-flop to settle in SET state.

→When both the SET and RESET input are high, the flip-flop  will be undefined state. Because the high inputs of S and R violate the rule of flip-flop the the outputs should complement to each other. So the flip-flop is in undefined state ( or forbidden state).

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