What are the major drawbacks to the use of asynchronous counter is dead
Answers
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Disadvantages
Area overhead caused by an increase in the number of circuit elements (transistors). In some cases an asynchronous design may require up to double the resources of a synchronous design, due to addition of completion detection and design-for-test circuits.
Fewer people are trained in this style compared to synchronous design.
Synchronous designs are inherently easier to test and debug than asynchronous designs. However, this position is disputed by Fant, who claims that the apparent simplicity of synchronous logic is an artifact of the mathematical models used by the common design approaches.
Clock gating in more conventional synchronous designs is an approximation of the asynchronous ideal, and in some cases, its simplicity may outweigh the advantages of a fully asynchronous design.
Performance (speed) of asynchronous circuits may be reduced in architectures that require input-completeness (more complex data path).
Lack of dedicated, asynchronous design-focused commercial EDA tools.