What is one disadvantage of an s-r flip-flop?
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The one major disadvantage of the s-r flip flop is that in the condition when the clock is triggered the inputs become high which is an undesirable condition because it causes invalid input ,the condition in which you can't predict the output. So, in short we can say that the outputs in S-r flip flop are undefined in that condition.
The one major disadvantage of the s-r flip flop is that in the condition when the clock is triggered the inputs become high which is an undesirable condition because it causes invalid input ,the condition in which you can't predict the output. So, in short we can say that the outputs in S-r flip flop are undefined in that condition.
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: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is referred to as Invalid State. Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1.
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