What would be the number of flipflop required to desingn mod 10 ring counter and mod 10 johnson counter respectively
Answers
In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of a Serial-in to Serial-out Shift Register, the same sequence of data will exit from the last flip flip in the register chain.
This serial movement of data through the resister occurs after a preset number of clock cycles thereby allowing the SISO register to act as a sort of time delay circuit to the original input data signal.
But what if we were to connect the output of this shift register back to its input so that the output from the last flip-flop, QD becomes the input of the first flip-flop, DA. We would then have a closed loop circuit that “recirculates” the same bit of DATA around a continuous loop for every state of its sequence, and this is the principal operation of a Ring Counter.
Then by looping the output back to the input, (feedback) we can convert a standard shift register circuit into a ring counter. Consider the circuit below.
4-bit Ring Counter
basic ring counter
The synchronous Ring Counter example above, is preset so that exactly one data bit in the register is set to logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is firstly applied to all the flip-flops together in order to “RESET” their outputs to a logic “0” level and then a “PRESET” pulse is applied to the input of the first flip-flop ( FFA ) before the clock pulses are applied. This then places a single logic “1” value into the circuit of the ring counter.
So on each successive clock pulse, the counter circulates the same data bit between the four flip-flops over and over again around the “ring” every fourth clock cycle. But in order to cycle the data correctly around the counter we must first “load” the counter with a suitable data pattern as all logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring counter invalid.
This type of data movement is called “rotation”, and like the previous shift register, the effect of the movement of the data bit from left to right through a ring counter can be presented graphically as follows along with its timing diagram:
Answer:
For n= 4,10<=16, which is true. Therefore the number of FF required is 4 for the Mod-10 counter.
Explanation:
In the last Shift Register lesson, we learned that the last flip-flop in the register chain would output the same sequence of data if a serial data signal is applied to the input of a Serial-in to Serial-out Shift Register.
After a certain number of clock cycles, serial data is moved through the resister, enabling the SISO register to function as a kind of time-delay circuit for the original input data signal.
The final flip-output, flop's QD, would then become the input of the first flip-flop, DA if the output of this shift register were to be connected back to its input. The main function of a Ring Counter is to create a closed loop circuit that "recirculates" the same bit of DATA around a continuous loop for each stage in its sequence.
Then by looping the output back to the input (feedback), we can convert a standard shift register circuit into a ring counter. Consider the circuit below.
4-bit Ring Counter
basic ring counter
The synchronous Ring Counter example above is preset so that exactly one data bit in the register is set to logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is first applied to all the flip-flops together to “RESET” their outputs to a logic “0” level, and then a “PRESET” pulse is applied to the input of the first flip-flop ( FFA ) before the clock pulses are applied. This then places a single logic “1” value into the circuit of the ring counter.
So on each successive clock pulse, the counter repeatedly circulates the same data bit between the four flip-flops around the “ring” every fourth clock cycle. But to cycle the data correctly around the counter, we must first “load” the counter with a suitable data pattern as all logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring counter invalid.
This type of data movement is called “rotation.” Like the previous shift register, the effect of the movement of the data bit from left to right through a ring counter can be presented graphically as follows along with its timing diagram: