Question

when J &K inputs of J & K flip flop are connected to logic one then the filp flop goes to state after clock is received A)Last State.
B) Toggle State.
C)Forbidden state.
D)None of this.​

Answer 1

Explanation:

However, if both the J and K inputs are HIGH at logic “1” (J = K = 1), when the clock input goes HIGH, the circuit will “toggle” as its outputs switch and change state complementing each other. This results in the JK flip-flop acting more like a T-type toggle flip-flop when both terminals are “HIGH”