Why different metal wires are used in metal layer stack?
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There are different metal layers which we uses in our design. As we move down the technology node number of standard cells increases or you can say that number of connections increases drastically. As all of us know that these connection are made of Metal wire, it means number of metal wires increases. Below figure help you to understand the scenario.
Case1 : I didn't decrease the size of the chip (despite change in the no of standard cells per unit area) as we go down the technology node. You can see that number of metal wires increases. Silicon utilization improves with improved routability. But these numbers (standard cell) increases 4 times (per node if we are decreases the size by 1/2, overall area decreases by 1/2*1/2=1/4). With available options of metal wire in higher node, it's difficult to route the same design in lower technology node. And that's the reason as we go down number of metal wires increases (vertically also).
Case 2: This is the real scenario. As Technology node decreases, no of standard cells increases and also chip size decreases. So you can imagine how difficult it is to route the design with a single metal wire or say on a single level. That's the reason we have multiple levels of metal wires. These levels are in vertical direction. As we go down the technology node, these levels increases. So you can say that down the technology node, size of the chip decreases in one dimension (in 2D) but increases in other dimension (vertically). :) :)
Case1 : I didn't decrease the size of the chip (despite change in the no of standard cells per unit area) as we go down the technology node. You can see that number of metal wires increases. Silicon utilization improves with improved routability. But these numbers (standard cell) increases 4 times (per node if we are decreases the size by 1/2, overall area decreases by 1/2*1/2=1/4). With available options of metal wire in higher node, it's difficult to route the same design in lower technology node. And that's the reason as we go down number of metal wires increases (vertically also).
Case 2: This is the real scenario. As Technology node decreases, no of standard cells increases and also chip size decreases. So you can imagine how difficult it is to route the design with a single metal wire or say on a single level. That's the reason we have multiple levels of metal wires. These levels are in vertical direction. As we go down the technology node, these levels increases. So you can say that down the technology node, size of the chip decreases in one dimension (in 2D) but increases in other dimension (vertically). :) :)
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