Why does DMA have priority over the CPU
when both request a memory transfer of
data ?
Answers
Answer:
Explanation:
Because the CPU always has access to the memory bus when a DMA transfer is not taking place, DMA appears to have priority. DMA operates by "cycle stealing" memory bus access cycles from the CPU. This has to do with the memory controller's role in the data transmission between the cache and memory on contemporary processors. The CPU cores can keep processing commands and using the cache.
Priority must be given to DMA to avoid over- and underrunning. The main applications of DMA are input and output.
Input from an unbuffered device does not enter memory if the bytes are not caught in time. We refer to this as overrun. The input was more than the system could handle. There was an input mistake. It requires a correction
Underrun occurs when a computer fails to deliver information on time when an unbuffered device is accepting output. This might result in unexpected 1s or 0s being sent on a communications line, gaps appearing on a plot, etc.
It should be noted that each cycle-steal only lasts as long as a few bytes are being transferred, not a full I/O block. Let's imagine the DMA has a 1024-byte capacity. The priority only applies to a single transfer of 8 bytes, not the entire set of 128 transfers, if the bus is, let's say, 8 bytes wide.
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