Why drain current is constant in saturation region?
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Consider now the behavior of drain current ID vs drain source voltage VDS. The gate source voltage is zero therefore VGS= 0. Suppose that VDS is gradually linearly increased linearly from 0V. IDalso increases.
Since the channel behaves as a semiconductor resistance, therefore it follows ohm's law. The region is called ohmic region, with increasing current, the ohmic voltage drop between the source and the channel region reverse biased the junction, the conducting portion of the channel begins to constrict and ID begins to level off until a specific value of VDSis reached, called the pinch of voltage VP.
At this point further increase in VDS do not produce corresponding increase in ID. Instead, as VDS increases, both depletion regions extend further into the channel, resulting in a no more cross section, and hence a higher channel resistance. Thus even though, there is more voltage, the resistance is also greater and the current remains relatively constant. This is called pinch off or saturation region. The current in this region is maximum current that FET can produce and designated by IDSS. (Drain to source current with gate shorted).

Fig. 3
As with all pn junctions, when the reverse voltage exceeds a certain level, avalanche breakdown of pn junction occurs and IDrises very rapidly as shown in fig. 3.
Consider now an N-channel JFET with a reverse gate source voltage as shown in fig. 4.

Fig. 4

Fig. 5
The additional reverse bias, pinch off will occur for smaller values of | VDS |, and the maximum drain current will be smaller. A family of curves for different values of VGS(negative) is shown in fig. 5.
Suppose that VGS= 0 and that due of VDS at a specific point along the channel is +5V with respect to ground. Therefore reverse voltage across either p-n junction is now 5V. If VGS is decreased from 0 to –1V the net reverse bias near the point is 5 - (-1) = 6V. Thus for any fixed value of VDS, the channel width decreases as VGS is made more negative.
Thus ID value changes correspondingly. When the gate voltage is negative enough, the depletion layers touch each other and the conducting channel pinches off (disappears). In this case the drain current is cut off. The gate voltage that produces cut off is symbolized VGS(off) . It is same as pinch off voltage.
Since the gate source junction is a reverse biased silicon diode, only a very small reverse current flows through it. Ideally gate current is zero. As a result, all the free electrons from the source go to the drain i.e. ID = IS. Because the gate draws almost negligible reverse current the input resistance is very high 10's or 100's of M ohm. Therefore where high input impedance is required, JFET is preferred over BJT. The disadvantage is less control over output current i.e. FET takes larger changes in input voltage to produce changes in output current. For this reason, JFET has less voltage gain than a bipolar amplifier
Since the channel behaves as a semiconductor resistance, therefore it follows ohm's law. The region is called ohmic region, with increasing current, the ohmic voltage drop between the source and the channel region reverse biased the junction, the conducting portion of the channel begins to constrict and ID begins to level off until a specific value of VDSis reached, called the pinch of voltage VP.
At this point further increase in VDS do not produce corresponding increase in ID. Instead, as VDS increases, both depletion regions extend further into the channel, resulting in a no more cross section, and hence a higher channel resistance. Thus even though, there is more voltage, the resistance is also greater and the current remains relatively constant. This is called pinch off or saturation region. The current in this region is maximum current that FET can produce and designated by IDSS. (Drain to source current with gate shorted).

Fig. 3
As with all pn junctions, when the reverse voltage exceeds a certain level, avalanche breakdown of pn junction occurs and IDrises very rapidly as shown in fig. 3.
Consider now an N-channel JFET with a reverse gate source voltage as shown in fig. 4.

Fig. 4

Fig. 5
The additional reverse bias, pinch off will occur for smaller values of | VDS |, and the maximum drain current will be smaller. A family of curves for different values of VGS(negative) is shown in fig. 5.
Suppose that VGS= 0 and that due of VDS at a specific point along the channel is +5V with respect to ground. Therefore reverse voltage across either p-n junction is now 5V. If VGS is decreased from 0 to –1V the net reverse bias near the point is 5 - (-1) = 6V. Thus for any fixed value of VDS, the channel width decreases as VGS is made more negative.
Thus ID value changes correspondingly. When the gate voltage is negative enough, the depletion layers touch each other and the conducting channel pinches off (disappears). In this case the drain current is cut off. The gate voltage that produces cut off is symbolized VGS(off) . It is same as pinch off voltage.
Since the gate source junction is a reverse biased silicon diode, only a very small reverse current flows through it. Ideally gate current is zero. As a result, all the free electrons from the source go to the drain i.e. ID = IS. Because the gate draws almost negligible reverse current the input resistance is very high 10's or 100's of M ohm. Therefore where high input impedance is required, JFET is preferred over BJT. The disadvantage is less control over output current i.e. FET takes larger changes in input voltage to produce changes in output current. For this reason, JFET has less voltage gain than a bipolar amplifier
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