Question

With the help of schematic, explain dynamic ckts.

Answer 1

Hyy,

Dynamic gates operate in two phases: precharge and evaluation. During the precharge phase, the clock is low, turning on the PMOS device and pulling the output high. During evaluation, the clock is high, turning off the PMOS device. The output may “evaluate” low through the NMOS transistor stack.

The PRECHARGE rule of dynamic gates states that there should be no active path to

The PRECHARGE rule of dynamic gates states that there should be no active path to ground during precharge, so that the PMOS transistor can fully precharge the output high

The PRECHARGE rule of dynamic gates states that there should be no active path to ground during precharge, so that the PMOS transistor can fully precharge the output high without contention with the NMOS pulldowns. Sometimes this can be achieved by guar-

The PRECHARGE rule of dynamic gates states that there should be no active path to ground during precharge, so that the PMOS transistor can fully precharge the output high without contention with the NMOS pulldowns. Sometimes this can be achieved by guar- anteeing that some inputs are low. For example, with a NOR4 gate, all four inputs must be low. For a NAND4 gate, only one of the series pulldown transistors must be low. It is not always possible to guarantee this condition, so often an extra clocked evaluation transistor is placed at the bottom of the pulldown stack, as shown in Figure 2.

FIGURE 2. Dynamic gates with and without clocked evaluation transistors.

Another limitation of dynamic gates arises when one dynamic gate directly drives the

Another limitation of dynamic gates arises when one dynamic gate directly drives the next, as shown in Figure 3. When φ is low, both gates precharge high. When φ rises, both

Another limitation of dynamic gates arises when one dynamic gate directly drives the next, as shown in Figure 3. When φ is low, both gates precharge high. When φ rises, both gates begin evaluating. Since the first gate has a high input, its output X falls low. The sec-

Another limitation of dynamic gates arises when one dynamic gate directly drives the next, as shown in Figure 3. When φ is low, both gates precharge high. When φ rises, both gates begin evaluating. Since the first gate has a high input, its output X falls low. The sec- ond NOR gate should therefore produce a high output. Unfortunately, the second NOR

Another limitation of dynamic gates arises when one dynamic gate directly drives the next, as shown in Figure 3. When φ is low, both gates precharge high. When φ rises, both gates begin evaluating. Since the first gate has a high input, its output X falls low. The sec- ond NOR gate should therefore produce a high output. Unfortunately, the second NOR gate initially received the high value at X and evaluates low. By the time X falls, Y may

Another limitation of dynamic gates arises when one dynamic gate directly drives the next, as shown in Figure 3. When φ is low, both gates precharge high. When φ rises, both gates begin evaluating. Since the first gate has a high input, its output X falls low. The sec- ond NOR gate should therefore produce a high output. Unfortunately, the second NOR gate initially received the high value at X and evaluates low. By the time X falls, Y may have become corrupted. Since the precharge transistors are off, Y has no way of recovering

Another limitation of dynamic gates arises when one dynamic gate directly drives the next, as shown in Figure 3. When φ is low, both gates precharge high. When φ rises, both gates begin evaluating. Since the first gate has a high input, its output X falls low. The sec- ond NOR gate should therefore produce a high output. Unfortunately, the second NOR gate initially received the high value at X and evaluates low. By the time X falls, Y may have become corrupted. Since the precharge transistors are off, Y has no way of recovering to the correct high value during the evaluation phase. The circuit produces an incorrect

Another limitation of dynamic gates arises when one dynamic gate directly drives the next, as shown in Figure 3. When φ is low, both gates precharge high. When φ rises, both gates begin evaluating. Since the first gate has a high input, its output X falls low. The sec- ond NOR gate should therefore produce a high output. Unfortunately, the second NOR gate initially received the high value at X and evaluates low. By the time X falls, Y may have become corrupted. Since the precharge transistors are off, Y has no way of recovering to the correct high value during the evaluation phase. The circuit produces an incorrect result.

☆☆HOPE IT MAY HELP YOU.☆☆