Question

Write the VHDL code for making Half Adder​

Answer 1

Explanation:

VHDL code for half adder using Dataflow modelling: library ieee; use ieee.std_logic_1164.all; entity half_adder is.

VHDL code for half adder using Structural modelling: library ieee; use ieee.std_logic_1164.all;

VHDL code for half adder using Behavioral modelling: library ieee; use ieee.std_logic_1164.all;

Answer 2

Now, we’ll write a VHDL program, compile and simulate it, and get the output in a waveform. We’ll also verify the output waveforms with the given truth table.

However, first it’s important to review the step-by-step procedure provided in VHDL Tutorial – 3. In that tutorial, we learn how to design a project, edit and compile a program, create a waveform file, simulate the program, and generate the final output waveforms.

VHDL program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is

port ( a,b : in std_logic;

sum,cry: out std_logic

);

end half_adder;

architecture adder_arch of half_adder is

begin

sum <= a xor b;

cry <= a and b;

end adder_arch;

Note:

“entity” describes the input-output connections of the digital circuit. As per the circuit given above, we have two inputs ‘a,’ ‘b,’ and two outputs, ‘sum’ and ‘cry.’

“architecture” describes the operation of the circuit, which refers to how the output is generated from the given input.

To refresh your memory about how this works, go through the first two VHDL tutorials (1 and 2) of this series.

Next, compile the above program, creating a waveform file with all of the necessary inputs and outputs that are listed, and simulate the project.

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