Question

You need to design a simple CISC architecture to carry out conversion of an 8-bit Binary number to 8-bit Gray
code number and vice-versa. Verify the Verilog code in Modelsim simulator by writing a test bench.
While designing architecture for binary code to gray code, use following parameters. A similar approach has to
be used to carry out the conversion of gray code to binary code. Valid assumptions, if made, need to be specified
clearly.
Parameters:
1. Define two 8 bit PIPO (Parallel In Parallel Out) registers (R1 and R2); R1 (for storing the binary number),
R2 (for storing the gray coded number), and two one bit registers (R3, R4) for holding 1 bit values to be
xored.
● Each register will have two input (flags): R1_in, R1_out
● When R1_in is high, register can take data from the external bus.
● When R1_out is high, register can send data to the external bus.
2. You can use only one XOR gate.
3. The interconnect structure should be implemented using tri sate buffers and MUXs so as to avoid bus
contention.
4. Define a Control Unit for controlling the process flow.
● It will have three inputs: Start, Convert and Clock. The Convert signal, if ‘0’ controls binary to
gray code conversion else gray to binary code conversion
● Output: R1_in, R1_out, R2_in, R2_out, R3_in, R3_out, R4_in, R4_out, and Done.
● When Start is high, process will start, else R2 register will hold 8 ’bzzzzzzzz value
● Done will go high when conversion is done and gray coded number is stored in R2, else will
remain in low.
● Use only Moore based FSM style for designing this control unit.

Answer 1

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