Question

1. For a ratioed logic, the pull up device is
A. Single, normally on load
B. Multiple loads
C. Normally OFF Loads
D. Depletion Mode NMOSFET

2. In a DCVSL style of sequential design, two pull-down networks should be
A. Matched
B. Complementary
C. Mutually Exclusive
D. Supplementary

3. For a pass transistor logic (PTL), the primary input are applied to
A. Source
B. Drain
C. Gate
D. Substrate

4. Pass Transistor Logic is characterized by signal degradation. One of the methods for signal restoration is
A. Static Inverter Insertion
B. Dynamic CMOS Insertion
C. Output connected to power supply
D. Output directly connected to ground.

5. In a level restoration circuit, with increasing width of the restoring transistor, for the input going from low to high, the output voltage
A. Goes Low
B. Goes High
C. No Change
D. Cannot be predicted

6. point Transmission Gate is a good transmitter of
A. 0
B. 1
C. both zero and one
D. none of zero and one

7. For an n-input dynamic logic the number of gates for full functionality is given as
A. n
B. n+2
C. n+4
D. 2n

8. The static power dissipation of an ideal N-gate dynamic logic is
A. 1 Watt
B. 0 Watt
C. N Watt
D. 2N Watt

9. For a pseudo NMOS logic working such that pull up PMOS is connected supply voltage of VDD and the pull down network is connected to ground. In such a scenario, the value of the nominal pull down voltage is
A. VDD
B. Zero
C. Just larger than zero volt
D. cannot be predicted with the information provided

10. For a static CMOS inverter, when the aspect ratio of the pull down network is increased, then which of the following statement is true
A. TpHLincreases
B. NML increases
C. NMH increases
D. TPLH increases

Answer 1

1. For a ratioed logic, the pull up device is  

A. Single, normally on load  

B. Multiple loads  

C. Normally OFF Loads  

D. Depletion Mode NMOSFET

Answer 2

1. For a ratioed logic, the pull up device is A. Single, normally on load B. Multiple loads C. Normally OFF Loads D. Depletion Mode NMOSFET  

A.1 - A. Single, normally on load

2. In a DCVSL style of sequential design, two pull-down networks should be A. Matched B. Complementary C. Mutually Exclusive D. Supplementary  

A.2 - B. Complementary

3. For a pass transistor logic (PTL), the primary input are applied to A. Source B. Drain C. Gate D. Substrate  

A.3 - C. Gate

4

4. Pass Transistor Logic is characterized by signal degradation. One of the methods for signal restoration is A. Static Inverter Insertion B. Dynamic CMOS Insertion C. Output connected to power supply D. Output directly connected to ground.  

A.4 - A. Static Inverter Insertion

5. In a level restoration circuit, with increasing width of the restoring transistor, for the input going from low to high, the output voltage A. Goes Low B. Goes High C. No Change D. Cannot be predicted  

A.5 - B. Goes High

6. point Transmission Gate is a good transmitter of A. 0 B. 1 C. both zero and one D. none of zero and one  

A.6 - C. both zero and one

7. For an n-input dynamic logic the number of gates for full functionality is given as A. n B. n+2 C. n+4 D. 2n  

A.7 - B. n+2  

8. The static power dissipation of an ideal N-gate dynamic logic is A. 1 Watt B. 0 Watt C. N Watt D. 2N Watt

A.8 B. 0 Watt

 

9. For a pseudo NMOS logic working such that pull up PMOS is connected supply voltage of VDD and the pull down network is connected to ground. In such a scenario, the value of the nominal pull down voltage is A. VDD B. Zero C. Just larger than zero volt D. cannot be predicted with the information provided  

A.9 C. Just larger than zero volt

10. For a static CMOS inverter, when the aspect ratio of the pull down network is increased, then which of the following statement is true A. TpHLincreases B. NML increases C. NMH increases D. TPLH increases

A.10 TPLH increases