A 4 bit modulo 16 ripple counter uses jk flip flops. If the propagation delay of each flip flop is 50nanosecond , the maximum clock frequency that can be used is equal to
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td is 50ns
total propagtion delay is 4x50ns =200ns (4 is number of flops in modulo 16)
then maximum clock frequency is given by
F=1/200x10^-9
F=5 MHz
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Concept:
- To get the overall delay in the counter, the propagation delays of all flip-flops are added
- The following clock pulse must arrive when all the carry's formed are propagated through all flip-flops and there is a stable output.
- Tclk≥n(tpd)FF
- fclk≤1/n(tpd)FF
Given:
- 4 bit modulo 16 ripple counter uses 5JK flip flops
- propagation delay = 50 nanosecond
Find:
- The maximum clock frequency that can be used
Solution:
Total propagation delay = 4*50 = 200 nanoseconds
Maximum frequency = 1/n(tpd)FF = 1/200 nanoseconds = 5 Mega Hz
5MHz is the maximum clock frequency that can be used.
#SPJ2
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