Question

Consider a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter (R) and assume that the output node is connected to / identical NOR gates. (a) Sketch the 3-input NOR gate (only the driver) with transistor sizes mentioned for achieving effective rise and fall resistance equal to that of a unit inverter. (b) Annotate the NOR gate (only the driver) with its gate and diffusion capacitances. Assume all diffusion nodes are contacted. (c) Sketch equivalent circuits by removing the capacitances whose both terminals are shortened. (d) Sketch separate circuits for falling output transition (best and worst-cases) and rising output transition. Also, derive the equations for falling (worst-case) and rising propagation delays at the output node.
Consider a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter (R) and assume that the output node is connected to / identical NOR gates. (a) Sketch the 3-input NOR gate (only the driver) with transistor sizes mentioned for achieving effective rise and fall resistance equal to that of a unit inverter. (b) Annotate the NOR gate (only the driver) with its gate and diffusion capacitances. Assume all diffusion nodes are contacted. (c) Sketch equivalent circuits by removing the capacitances whose both terminals are shortened. (d) Sketch separate circuits for falling output transition (best and worst-cases) and rising output transition. Also, derive the equations for falling (worst-case) and rising propagation delays at the output node.

Answer 1

Answer:

Transcribed image text: Question 2: Consider a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter (R) and assume that the output node is connected to h identical NOR gates (a) Sketch the 3-input NOR gate (only the driver) with transistor sizes mentioned for achieving effective rise and fall resistance equal to that of a unit inverter. (b) Annotate the NOR gate (only the driver) with its gate and diffusion capacitances. Assume all diffusion nodes are contacted. (c) Sketch equivalent circuits by removing the capacitances whose both terminals are shortened. (d) Sketch separate circuits for falling output transition (best and worst-cases) and rising output transition. Also, derive the equations for falling (worst-case) and rising propagation delays at the output node.

Explanation: