Difference between static cmos and dynamic cmos in vlsi
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Hiiii dude.....
Static logic is slower because it has twice the capacitive loading, higher thresholds, and uses slow P transistors for logic. ... In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS.
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The difference between static CMOS and dynamic CMOS in VLSI :
- Static CMOS circuits use or utilise complementary nMOS pulldown.
- And pMOS pull-up networks to implement logic gates or logic functions in integrated circuits.
- Dynamic gates use a clocked pMOS pullup.
- The enforced logic performs or the gate is achieved through 2 modes of operation: Precharge and choose.
- This is the main difference between static CMOS and dynamic CMOS.
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