Question

Distinguish between vector and non vectored interrupt of a microprocessor

Answer 1

Answer:

Explanation:

Vectored Interrupts

Devices that use vectored interrupts are assigned an interrupt vector. This is a number that identifies a particular interrupt handler. The ISR address of this interrupts is fixed and is known to CPU.

When the device interrupts the CPU branches to the particular ISR.

The microprocessor jumps to the specific service routine.

When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack.

At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.

All 8051 interrupts are vectored interrupts.

Non-vectored Interrupt

Non-vectored interrupt is an interrupt that has a common ISR, which is common to all non-vectored interrupts in the system. Address of this common ISR is known to the CPU.

The interrupts which don’t have fixed memory location for transfer of control from normal execution.

The address of the memory is sent along with the interrupt.

The CPU crucially does not know which device caused the interrupt without polling each I/O interface in a loop.

Once the interrupt occurs, the system must determine which device, of all the devices associated actually interrupted.

The Difference

A vectored interrupt is where the CPU actually knows the address of the interrupt service routine in advance. All it needs is that the interrupting device sends its unique vector through a data bus and through its I/O interface to the CPU. The CPU takes this vector, checks an interrupt table in memory and then carries out the correct ISR for that device. Therefore, the vectored interrupt allows the CPU to be able to know that ISR to carry out in software (memory)             .

A non–vectored interrupt is where the interrupting device never sends an interrupt vector. An interrupt is received by the CPU and it jumps the program counter to a fixed address in hardware. This is typically a hard coded ISR which is device agnostic. The CPU crucially does not know which device caused the interrupt without polling each O/I interface in a loop and checking the status register of each I/O interface to find the one with status “interrupt created”.