Question

draw the logic diagram of a four bit binary ripple count down counter using flip flops that trigger on the positive edge of the clock​

Answer 1

The 4 Q outputs of the flip flops are at first 0000. At the point when the rising edge of the clock beat is connected to the FF0, at that point the output Q0 will change to logic 1 and the following clock pulse will change the Q0 yield to rationale / logic 0. This implies the output condition of the clock beat flips (changes from 0 to1) for one cycle.  

As the Q' of FF0 is associated with the clock contribution of FF1, at that point the clock contribution of second flip flop will progress and will become 1. This makes the yield of FF1 to be high (for example Q1 = 1), which shows the esteem 20. Along these lines the following clock pulse will make the Q0 to turn out to be high once more.  

So now both Q0 and Q1 are high, this outcomes in making the 4 bit output 11002. Presently in the event that we apply the fourth clock beat, it will make the Q0 and Q1 to low state and flips the FF2. So the yield Q2 will end up 0010¬2.