Question

Explain the performance of instruction pipelines with reference to Stalling and Forwarding
method. (5 Marks)​

Answer 1

Explanation:

In the design of pipelined computer processors, a pipeline stall is a delay in execution of an instruction in order to resolve a hazard.[1]

In a standard five-stage pipeline, during the decoding stage, the control unit will determine if the decoded instruction reads from a register that the instruction currently in the execution stage writes to. If this condition holds, the control unit will stall the instruction by one clock cycle. It also stalls the instruction in the fetch stage, to prevent the instruction in that stage from being overwritten by the next instruction in th