How many clock pluses required to load 4 bit SIPO register and transfer the data to a output register?
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16 clock pluses required to load 4 bit SIPO register and transfer the data to a output register?
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Answer:
n clock are used to load the data in shift register SIPO ,where n is no.of flip flop.As it is 4 bit SIPO so ,n=4.
4 clock are required to load the data in SIPO and There no clock are required to transfer the data to output because we are taking data parallel .
ie overall process will be done by 4 clock.
Explanation:
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