Question

NPTEL Online Course

Course: CMOS Digital VLSI Design

Assignment-5

Due date for this assignment: 2019-04-03, 23:59 IST.

1. Which of the following statement is true for high impedance nodes?
A). May be modeled as a open circuit
B). May be modeled as a closed circuit
C). These nodes can be verified by voltage measurement alone
D). They are not floating nodes

2. Assuming Wn and Wp to be widths of the NMOS and PMOS transistors of a Domino CMOS Logic, the value of tPHL (high-to-low propagation delay) is equal to
A). Wn/Wp
B). Wp/Wn
C). Zero
D). Wn + Wp

3. For a 180 nm process the value of the unit delay is approximately
A). 100 ps
B). 12 ps
C). 35 ps
D). 55 ps

4. If the output and the input capacitance of logic is Cout and Cin respectively then the value of electrical effort is
A). Cin /Cout
B). Cout /Cin
C). 2Cin /Cout
D). 2Cout /Cin

5. Find the value of the logical effort of a NOR-2 gate whose delay is equivalent to a CMOS inverter whose Wp/Wn = 3/1, where Wp and Wn are the widths of the PMOS and NMOS respectively
A). 5/3
B). 7/3
C). 11/5
D). 7/4
E). 1 point

6. A NAND-2 gate drives a NOR-2 gate of equal dimensions and capacitive loading, then the logical effort of the compound network will be
A). 20/9
B). 25/3
C). 30/7
D). 35/7

7. For a three stage digital logic design using NAND, NOR and MUX, in series, the total parasitic delay is 8 unit and the best stage effort is 6. The total delay from primary input to output is
A). 27
B). 25
C). 26
D). 21

8. The frequency of an N stage ring oscillator with the following parameters: Logical effort = Branching Effort = Electrical Effort = parasitic delay = 1 units and delay = 3 units is
A). 1/4N
B). 4N
C). 6N
D). 1/6N

9. The time before the rising/falling clock edge till which the data must be stable for proper sampling of the data is referred to as
A). Set-up Time
B). Hold Time
C). Clock Period
D). Tc-q delay

10. Memories based on positive feedback falls under the class of
A). Astable Circuits
B). Bistable Circuits
C). Multivibrators
D). Dynamic Circuits

Answer 1

Plz ask ur questions one by one.

✌✌

Answer 2

A). May be modeled as an open circuit.

D). Wn + Wp.

C). 35 ps.

A). Cin/Cout.

B). 7/3.

A). 20/9.

C). 26.

A). 1/4N.

A). Set-up Time.

B). Bistable Circuits.

High-impedance nodes can be modeled as an open circuit.tPHL (high-to-low propagation delay) for Domino CMOS Logic is equal to Wn + Wp.The value of the unit delay for a 180 nm process is approximately 100 ps.The value of electrical effort for logic with output capacitance Cout and input capacitance Cin is Cout/Cin.The logical effort of a NOR-2 gate with a delay equivalent to a CMOS inverter is 7/4.The logical effort of a compound network composed of a NAND-2 gate driving a NOR-2 gate is 30/7.The total delay from primary input to output for a three-stage digital logic design using NAND, NOR, and MUX in series with a total parasitic delay of 8 units and a best stage effort of 6 is 26.The frequency of an N-stage ring oscillator with logical effort, branching effort, electrical effort, parasitic delay of 1 unit, and delay of 3 units is 1/4N.The time before the rising/falling clock edge till which the data must be stable for proper sampling of the data is referred to as hold time.Memories based on positive feedback fall under the class of bistable circuits.

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