What are the basic instruction between a brance instruction, a call subrouting instruction and program interrupt?
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Step 1 of 5
Consider the following figure 8-2, in which 7 register and a destination decoder and an ALU. The output in the given figure is connected to two multiplexer (MUX) to form two buses A and B. The input data for particular bus or one register is selected by the selection lines in the multiplexer.
In the same way consider that bus-organized CPU, similar to the above discussed figure, has 16 registers and each register contains 32 bits in each, an Arithmetic Logic Unit (ALU) and a decoder which acts as a destination decoder.
• Then the number of multiplexer contained in A-bus will be 32 multiplexer.
• The size of each multiplexer will be 16*1
Step 2 of 5
Consider the following figure 8-2, in which 7 register and a destination decoder and an ALU. The output in the given figure is connected to two multiplexer (MUX) to form two buses A and B. The input data for particular bus or one register is selected by the selection lines in the multiplexer.
In the same way consider that bus-organized CPU, similar to the above discussed figure, has 16 registers and each register contains 32 bits in each, an Arithmetic Logic Unit (ALU) and a decoder which acts as a destination decoder.
• For MUX A, the number of selection inputs are needed is four, to select one of the selection register.
• For MUX B, the number of selection inputs are needed is four, to select one of the selection register.
Step 3 of 5
Consider the figure 8-2, in which decoder is used which acts as 3 to 1 decoder. In the same way when a bus-organized CPU, similar to the above discussed figure, has 16 registers and each register contains 32 bits in each, an Arithmetic Logic Unit (ALU) and a decoder which acts as a destination decoder.
In other words, the number of inputs in the decoder in sixteen and the outputs in the decoder is four.
Step 4 of 5
The number of input including input carries in the ALU for data can be obtained as:
• Number of data input lines:
32+32+1=65 data input lines.
The number of output including output carries in the ALU for data can be obtained as:
• Number of data output lines:
32+1=33 data output lines.
Step 5 of 5
Consider the following control word, the following control word is formulated for the system considering that there are thirty operations in the ALU.
4 4 4 6
SEL A
SEL B
SEL D
OPR
The 18-bit control word which is defined above consists four fields. The three bits contains four bit each and one field contains six bit.
• The selection of a source register for the A input of the ALU is performed by these four bits of SEL A.
• The selection of a source register for the B input of the ALU is performed by these four bits of SEL B.
• The four bits of the SEL D select a destination register using the decoder and its input.
• The six bits of OPR select one of the operations in the ALU.
When these 18-bit control word is applied to the selection inputs then it will denotes a particular micro operations.
Consider the following figure 8-2, in which 7 register and a destination decoder and an ALU. The output in the given figure is connected to two multiplexer (MUX) to form two buses A and B. The input data for particular bus or one register is selected by the selection lines in the multiplexer.
In the same way consider that bus-organized CPU, similar to the above discussed figure, has 16 registers and each register contains 32 bits in each, an Arithmetic Logic Unit (ALU) and a decoder which acts as a destination decoder.
• Then the number of multiplexer contained in A-bus will be 32 multiplexer.
• The size of each multiplexer will be 16*1
Step 2 of 5
Consider the following figure 8-2, in which 7 register and a destination decoder and an ALU. The output in the given figure is connected to two multiplexer (MUX) to form two buses A and B. The input data for particular bus or one register is selected by the selection lines in the multiplexer.
In the same way consider that bus-organized CPU, similar to the above discussed figure, has 16 registers and each register contains 32 bits in each, an Arithmetic Logic Unit (ALU) and a decoder which acts as a destination decoder.
• For MUX A, the number of selection inputs are needed is four, to select one of the selection register.
• For MUX B, the number of selection inputs are needed is four, to select one of the selection register.
Step 3 of 5
Consider the figure 8-2, in which decoder is used which acts as 3 to 1 decoder. In the same way when a bus-organized CPU, similar to the above discussed figure, has 16 registers and each register contains 32 bits in each, an Arithmetic Logic Unit (ALU) and a decoder which acts as a destination decoder.
In other words, the number of inputs in the decoder in sixteen and the outputs in the decoder is four.
Step 4 of 5
The number of input including input carries in the ALU for data can be obtained as:
• Number of data input lines:
32+32+1=65 data input lines.
The number of output including output carries in the ALU for data can be obtained as:
• Number of data output lines:
32+1=33 data output lines.
Step 5 of 5
Consider the following control word, the following control word is formulated for the system considering that there are thirty operations in the ALU.
4 4 4 6
SEL A
SEL B
SEL D
OPR
The 18-bit control word which is defined above consists four fields. The three bits contains four bit each and one field contains six bit.
• The selection of a source register for the A input of the ALU is performed by these four bits of SEL A.
• The selection of a source register for the B input of the ALU is performed by these four bits of SEL B.
• The four bits of the SEL D select a destination register using the decoder and its input.
• The six bits of OPR select one of the operations in the ALU.
When these 18-bit control word is applied to the selection inputs then it will denotes a particular micro operations.
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