Question

what is disadvantage of sr flip flop?​

Answer 1

hey mate!

The one major disadvantage of the s-r flip flop is that in the condition when the clock is triggered the inputs become high which is an undesirable condition because it causes invalid input ,the condition in which you can't predict the output.

Answer 2

One of the main disadvantage of the basic sr flip flop circuit is that the indeterminate input condition of "SET" = logic " 0" and "reset" = Logic "0" is forbidden .

In simple words , R=S=0 or R= S = 1 , the output Q and Q ' either don't change or they are indeterminate ( invalid)

Hope you understand

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