What is the purpose of this command slow_vdd1v0_basiccells.Lib?
Answers
Answer:
17
ASIC Lab Manual © 2014 Cadence Design Systems, Inc
Once the script file to run synthesis and the constraints file are ready, we can initiate synthesis.
Use the below command to invoke RTL compiler along with the script file.
rc -f <script file name with path>
‘
rc
’
is the command to invoke RTL Compiler and ‘
-
f’ option is used to
passes the script to RC at the time of launching the tool. RC will execute each commands mentioned inside the script file one by one.
Note: -
If the script file is in the current working directory (synthesis directory), we need not have to provide the path for the script. E.g. - In case of the counter design, the command will be
‘rc
–
f
rc_script.tcl’
While performing synthesis, always check the RC terminal whether the tool is reporting any error. Figure below shows the RC terminal after synthesis.
After synthesis, to see the schematic, launch the gui using the below command.
‘
gui_show’
in the
‘rc’
terminal. Use
‘
gui_hide’
command to close the gui.