what will be the maximum value of a 4 bit adder circuit
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Answer:
The glib answer is “whatever the designer wants it to”.
When I started out looking at computer design in the late 1970s I had a background in mathematics and, to a lesser extent, in computer programming. Some of the early work I did involved the design and implementation of instruction sets, and in particular, of the arithmetic operations. All of this required that I had to build an understanding of computer arithmetic, and because of background, I did it from a slightly abstract, mathematical point of view. This was in contrast to what was laid out in a lot of electronics and computer design textbooks which set out functions (e.g. adders) and their implementation, but didn’t always give motivation.
The motivation for implementing an adder is to take two sets of bits (“words”), representing numbers, and to produce an output representing the sum of those bits. There are three of key questions to ask here. First, what are the numbers that we are trying to represent. Secondly, how are these numbers represented as bits. And thirdly, what is supposed to happen if the sum of the two numbers can’t be represented as a set of bits.
A common situation (N-bit, little endian, unsigned integer) is that an N-bit word is used to represent the integers [0,2^N-1], and the word B[N-1]...B[0] represents the value ΣB[i]2^i: i in [0,N-1]. The third question is an issue - the sum of the two inputs can be in the range [0,2*(2^N-1)] and so there are results which cannot be represented.
A simple textbook implementation of an “N-bit adder” builds it from N “1-bit full adders”. In addition to the 2 sets of N operand bits, there is a carry-in bit (forced to zero) and a carry-out bit. If the mathematical result of the addition can be represented, then the N-bits of result from the adder will be the correct representation of the result, and the carry-out will be 0. If, on the other hand, the mathematical result of the addition cannot be represented, then the N-bits of result from the adder will be the correct representation of the result modulo 2^N, and the carry-out will be 1. To summarise, this adder alway produces the correct result modulo 2^N and a carry out indicates the correct result is not representable. Some computer systems will want to treat this as an error, perhaps recording it in a flag, or causing an exception.
Another common situation (N-bit, little endian, signed two’s complement integer) is that an N-bit word is used to represent the integers [-2^(N-1),2^(N-1)-1], and the word B[N-1]...B[0] represents the value -B[N-1]*2^N + ΣB[i]2^i: i in [0,N-1]*. Again, there are results which cannot be represented. The adder described earlier produced the correct result for all the representable results (which is why twos complement arithmetic is used). However, the carry-out does not indicate whether the result is representable. (Consider -1 + 1 = 0 which produces a carry-out and 0+0=0 which does not). For two’s complement the condition which represents an unpresentable result (commonly called “overflow”) is that the sign-bit (most significant bit) of the result is “unexpected” - that is the sum of two negative numbers appears to be positive, or the sum of two positive numbers appears to be negative (exercise to the reader to show that the sum of two number of different signs can always be represented).
Some other representations may be able to use the same adders as signed and unsigned integers. For fractional representations where the value of a word is the value of the word, treated as an integer, divided by a power of two, the adder produces the correct result when the value is representable. However, in systems using these representations, sometimes the desired behaviour is that the results “saturate” - that is is the result is out of range, the sum is the most positive or the most negative value, as appropriate. Other systems 2 one of the values, (typically 10…0) for use as an error value which will then propagate through further operations. In this case a special adder will be needed.
* This formulation makes explicit the two’s complement form - the signed value of the word is the unsigned value of the word minus 2^N times the top bit (sign bit). Equivalently the value can be written -B[N-1]*2^(N-1) + ΣB[i]2^i: i in [0,N-2]which corresponds to the top bit representing 0 or -1 rather than 0 or +1.
Answer:
An adder, or summer,[1] is a digital circuit that performs addition of numbers. In many of the computers and other kinds of processors adders are used in the arithmetic logic units (ALUs). They are used in other parts of the processor, where they are used as a calculate address, table indices, increment and decrement operators and similar operations.
Although adders can be constructed for many of the number representations, such as binary-coded decimal or excess-3, the most common adders operate o\in binary number. In cases where two's complement or ones' complement is being used to represent negative numbers, it is a trivial to modify an adder into a adder–subtractor. Other signed number representations require more logic around the basic adder.
The half adder adds two of the single binary digits A and B. It has two output, sum (S) and carry (C). The carry signal represent an overflow into the next digit of a multi-digit addition. The value of sum is 2C + S. The simplest half-adder design, pictured on right, incorporates an XOR gate for S and an AND gate for C. Boolean logic for the sum (in the case S) will be A′B + AB′ whereas for carry (C) will be AB. With addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder.[2] The half adder adds input bits and generates a carry and sum, which are two outputs of a half adder. The input variables of a half adder are called the augend and addend bits. The output variables are sum and carry.
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