Question

which all stages in a 5-stage RISC-MIPS instruction pipeline access the cache memory?

Answer 1

The correct answer is option C.

IF ( Instruction Fetch ) and MEM ( memory access) stages in a 5-stage RISC-MIPS instruction pipeline access the cache memory.

The other 3 stages of a RISC MIPS instruction pipeline are -

ID ( Instruction Decode ) and EX ( Execute ) and WB ( write back ).

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Answer 2

IF and MEM are the stages access the cache memory.

Explanation:

• There are five instruction stages. They are as follows,

         1) Instruction Fetch (IF)

        2) Instruction Decode (ID)

        3) Execute (EX)

        4) Memory Access (MEM)

        5) Write Back (WB)

• IF – Here, the instruction can be fetched from memory (especially cache). The instructions are often seen in I-cache.  

• MEM is used for calculating effective addresses by considering base register and adding the offset. It is used for loading or storing the memory.

Learn more about RISC-MIPS instruction

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