Question

Which all stages in a 5-stage RISC-MIPS instruction pipeline access the cache memory?

Answer 1

The correct answer is option C.

IF ( Instruction Fetch ) and MEM ( memory access) stages in a 5-stage RISC-MIPS instruction pipeline access the cache memory.

The other 3 stages of a RISC MIPS instruction pipeline are -

ID ( Instruction Decode ) and EX ( Execute ) and WB ( write back ).

Answer 2

Answer:

MEM and Fetch stage

Explanation:

The five stages in RISC are Instruction Fetch, Instruction Decode, Execute, Memory access, Writeback.

Instruction fetch: This is a stage where the instruction is fetched from the memory. Here the memory points to the cache memory.  

Memory access:

Cache holds both data and instruction. In this stage the necessary data are collected and written back.

So among all five stages, RISC MIPS access the cache memory in the 1st and 4th stage.