Question

Why power dissipation in cmos chip is extremely small compare to nmos chip for the same number of gates.

Answer 1

in Cmos you have High Z input and active pull up and Pull down so you didn't have any static power usage and the only power usage is dynamic power usage( charging and discharging load capacitor). also CMOS is full swing technology ( in out put you have exact VDD ang GND) and the last thing you did not use any resistor in CMOS so the size of your circuit became very smallest.

Answer 2

Answer:

CMOS logic dissipates less power than NMOS logic circuits because CMOS dissipates power only when switching ("dynamic power"). ... Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips.