Question

You have to design a common bus system for a memory unit &ten registers. The memory unit and all the registers will have data input and output linesconnected to the bus. The memory unit will have read and writeinputs. The registers will have load inputs. All the registers will have a common clock pulse line. The memory unit will have an address input line from any one of the registers of your own preference. There will also be a selection / control unit with appropriatenumber of control lines.
You have to draw the circuit diagram along with necessary labeling for all types of lines present in the diagram.
You also have to give an explanation about how your drawn circuit diagram works in terms of sending and receiving data between memory unit and registers

Answer 1

Answer:

You have to design a common bus system for a memory unit &ten registers. The memory unit and all the registers will have data input and output linesconnected to the bus. The memory unit will have read and writeinputs. The registers will have load inputs. All the registers will have a common clock pulse line. The memory unit will have an address input line from any one of the registers of your own preference. There will also be a selection / control unit with appropriatenumber of control lines.

You have to draw the circuit diagram along with necessary labeling for all types of lines present in the diagram.

You also have to give an explanation about how your drawn circuit diagram works in terms of sending and receiving data between memory unit and registers