: how many priority modes are available in 8259? explain.
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Fully Nested Mode
This is the default mode of operation of 8259A. IR0 has the highest priority and IR7 has the lowest one. When interrupt requests are noticed,the highest priority request amongst them is determined and the vector is placed
on the data bus. The corresponding bit of ISR is set and remains set till the microprocessor issues an EOI command just before returning from the service routine or the AEOI bit is set. If the ISR (in service) bit is set, all the same or
lower priority interrupts are inhibited but higher levels will generate an interrupt, that will be acknowledged only if the microprocessor's interrupt enable flag (IF) is set. The priorities can afterwards be changed by programming the rotating priority modes.
End of Interrupt (EOI)
The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command, issued before returning from the interrupt service routine. There are two types of EOI commands specific and non-specific. When 8259A is
operated in the modes that preserve fully nested structure, it can determine which ISR bit is to be reset on EOT. When nonspecific EOI command is issued to 8259A it will automatically reset the highest ISR bit out of those already set. When a mode that may disturb the fully nested structure is used, the 8259A is no longer able to determine the last level acknowledged. In this case a specific EOI command is issued to reset a particular ISR bit. An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a non-specific EOI of 8259A, if it is in special mask mode.
Automatic Rotation
This is used in the applications where all the interrupting devices are of equal priority. In this mode, an interrupt request (IR) level receives lowest priority after it is served while the next device to be served gets the highest priority in sequence. Once all the devices are served like this, the first device again receives highest priority.
Automatic EOI Mode
Till AEOI = 1 in ICW4, the 8259A operates in AEOI mode. In this mode, the 8259A performs a non-specific EOI operation at the trailing edge of the last INTA pulse automatically. This mode should be used only when a nested multilevel interrupt structure is not required with a single 8259A.
Specific Rotation
In this mode a bottom priority level can be selected, using L2, L1 and L0in OCW2 and R =1, SL = 1, EOI = 0. The selected bottom priority fixes other priorities. If IR5 is selected as a bottom priority, then IR5 will have least priority and IR4 will have a next higher priority. Thus IR6 will have the highest priority. These priorities can be changed during an EOI command by programming the rotate on specific EOI command in OCW2
Special Mask Mode
In special mask mode, when a mask bit is set in OCWl, it inhibits further interrupts at that level and enables interrupt from other levels,which are not masked.
Edge and Level Triggered Mode
This mode decides whether the interrupt should be edge triggered or level triggered. If bit LTIM of ICWl = 0, they are edge triggered, otherwise the interrupts are level triggered.Reading 8259 Status The status of the internal registers of 8259A can be read using this mode. The OCW3 is used to read IRR and ISR while OCWl is used to
read IMR. Reading is possible only in no polled mode.
Poll Command
In polled mode of operation, the INT output of 8259A is neglected, though it functions normally, by not connecting INT output or by masking INT input of the microprocessor. The poll mode is entered by setting P =1 in OCW3. The 8259A is polled by using software execution by microprocessor instead of the requests on INT input. The 8259A treats the next RD pulse to the 8259A as an interrupt acknowledge. An appropriate ISR bit is set, if there is a
request. The priority level is read and a data word is placed on to data bus, after RD is activated. The data word is shown in Figure
A poll command may give you more than 64 priority levels. Note that this has nothing to do with the 8086 interrupt structure and the interrupt priorities.
Buffered Mode
When the 8259A is used in the systems where bus driving buffers are used on data buses (e.g. cascade systems). The problem of enabling the buffers exists. The 8259A sends buffer enable signal on SP /EN pin, whenever data is
placed on the bus.
This is the default mode of operation of 8259A. IR0 has the highest priority and IR7 has the lowest one. When interrupt requests are noticed,the highest priority request amongst them is determined and the vector is placed
on the data bus. The corresponding bit of ISR is set and remains set till the microprocessor issues an EOI command just before returning from the service routine or the AEOI bit is set. If the ISR (in service) bit is set, all the same or
lower priority interrupts are inhibited but higher levels will generate an interrupt, that will be acknowledged only if the microprocessor's interrupt enable flag (IF) is set. The priorities can afterwards be changed by programming the rotating priority modes.
End of Interrupt (EOI)
The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command, issued before returning from the interrupt service routine. There are two types of EOI commands specific and non-specific. When 8259A is
operated in the modes that preserve fully nested structure, it can determine which ISR bit is to be reset on EOT. When nonspecific EOI command is issued to 8259A it will automatically reset the highest ISR bit out of those already set. When a mode that may disturb the fully nested structure is used, the 8259A is no longer able to determine the last level acknowledged. In this case a specific EOI command is issued to reset a particular ISR bit. An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a non-specific EOI of 8259A, if it is in special mask mode.
Automatic Rotation
This is used in the applications where all the interrupting devices are of equal priority. In this mode, an interrupt request (IR) level receives lowest priority after it is served while the next device to be served gets the highest priority in sequence. Once all the devices are served like this, the first device again receives highest priority.
Automatic EOI Mode
Till AEOI = 1 in ICW4, the 8259A operates in AEOI mode. In this mode, the 8259A performs a non-specific EOI operation at the trailing edge of the last INTA pulse automatically. This mode should be used only when a nested multilevel interrupt structure is not required with a single 8259A.
Specific Rotation
In this mode a bottom priority level can be selected, using L2, L1 and L0in OCW2 and R =1, SL = 1, EOI = 0. The selected bottom priority fixes other priorities. If IR5 is selected as a bottom priority, then IR5 will have least priority and IR4 will have a next higher priority. Thus IR6 will have the highest priority. These priorities can be changed during an EOI command by programming the rotate on specific EOI command in OCW2
Special Mask Mode
In special mask mode, when a mask bit is set in OCWl, it inhibits further interrupts at that level and enables interrupt from other levels,which are not masked.
Edge and Level Triggered Mode
This mode decides whether the interrupt should be edge triggered or level triggered. If bit LTIM of ICWl = 0, they are edge triggered, otherwise the interrupts are level triggered.Reading 8259 Status The status of the internal registers of 8259A can be read using this mode. The OCW3 is used to read IRR and ISR while OCWl is used to
read IMR. Reading is possible only in no polled mode.
Poll Command
In polled mode of operation, the INT output of 8259A is neglected, though it functions normally, by not connecting INT output or by masking INT input of the microprocessor. The poll mode is entered by setting P =1 in OCW3. The 8259A is polled by using software execution by microprocessor instead of the requests on INT input. The 8259A treats the next RD pulse to the 8259A as an interrupt acknowledge. An appropriate ISR bit is set, if there is a
request. The priority level is read and a data word is placed on to data bus, after RD is activated. The data word is shown in Figure
A poll command may give you more than 64 priority levels. Note that this has nothing to do with the 8086 interrupt structure and the interrupt priorities.
Buffered Mode
When the 8259A is used in the systems where bus driving buffers are used on data buses (e.g. cascade systems). The problem of enabling the buffers exists. The 8259A sends buffer enable signal on SP /EN pin, whenever data is
placed on the bus.
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