Question

Verilog code for floating point multiplication

Answer 1

In the existing code you have this normalizing loop:



while (prod[22] == 0)
begin
prod = prod << 1;


There is nothing that handles the zero case in that loop (no counter to limit the number of shifts) so simulation will hang in this loop if prod is zero. Therefore you would need to place your code to handle the zero case before this loop like:



//postnormalize product
if (prod ==0)
begin
sum =32'b0;
else
begin
while (prod[22] == 0) // This will not synthesize!
begin
prod = prod << 1;
exp_unbiased = exp_unbiased - 1;
end
sign = sign_a ^ sign_b;
sum ={sign, exp_unbiased, prod};
end
end
Also I noted that the same while loop will not synthesize because it is unbounded (the compiler cannot determine at synthesis time how many iterations it can take to complete). It should be replaced with a for loop for synthesis. Somthing like:



for (i = 0; i < 22;i = i + 1)
if (prod[22] == 0)
begin
prod = prod << 1;
exp_unbiased = exp_unbiased - 1;
end
This example implements a loop of fixed iterations, however the if statement prevents any action from iterations after prod[22] has become 1.