Question

What is the limitation of internal memory?

Answer 1

As I understand it, something like an ALU would have a latch to keep the input data on the internal wiring / data paths until the next clock cycle. There are latches between every pipeline stage which accept new data on every clock cycle (assuming fully-pipelined ALUs, e.g. one-per-clock throughput with multi-cycle latency.) So the data isn't stored in any kind of "memory", other than the latches between pipeline stages. Mostly it's just live in the logic gates.
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