Question

Consider a uniprocessor with separate data and instruction caches, with hit ratios of and respectively. access time from processor to cache is c clock cycles, and transfer time for a block between memory and cache is b clock cycles. let be the fraction of memory accesses that are for instructions, and is the fraction of dirty lines in the data cache among lines replaced.assume a write-back policy

Answer 1

consider caches with hit and ratio is b clock and replaced by A clock the speed of nus is =45